This invention relates to detector circuits and in particular to MOS dectector circuits used in conjunction with dynamic memory systems.
One basic detector is essentially a flip-flop circuit in which current alternates from one leg to the other as a function of an input signal. Each leg contains an MOS load transistor in series with an MOS switching transistor. The gate of each switching transistor is cross-coupled to the drain of the other switching transistor. A DC voltage supply is applied to the common drains of the load transistors and an input signal is coupled to one of the gates of the switching transistors. One of the major problems of this detector is that power dissipation is relatively high since there is essentially always a flow of DC current.
The use of the basic MOS detector flip-flop with a pulsed voltage power supply reduces power dissipation. Ideally power should be turned off just after the proper output state is achieved. One difficulty is that a reasonable time span must be provided after the output is supposed to have reached the correct level in order to insure that in fact the correct level is achieved.
A detector circuit which automatically limits power dissipation at the time that the output signals reach the appropriate levels would be desirable.